rev. page date rev. page date description: dc-dc converter 1 of 3 01/2011 20050 sw 112 th ave. tualatin, oregon 97062 p h o n e phone 503.612.2300 f a x www.v-infinity.com fax 503.612.2383 series: vat1-smt features isolated 1 w output temperature range: -40c~+85c unregulated high efficiency to 79% dual voltage output small footprint smd package style industry standard pinout ul94-v0 package no heatsink required 1k vdc isolation high power density no external component required low cost description designed to convert fixed volt- ages into an isolated voltage, the vat1-smt series is well suited for providing board-mount local sup- plies in a wide range of applica- tions, including mixed analog/digi- tal circuits, test & measurement equip., process/machine controls, datacom/telecom fields, etc... the semi-regulated output can be followed by 3-terminal regulators to provide output protection, in addition to output regulation. output specifications item test conditions min. typ. max. units output power 0.1 1 w line regulation for vin change of 1% 1.2 % output voltage accuracy see tolerance envelope graph temperature drift @ 100% load 0.03 %/c output ripple 20 mhz bandwidth 50 75 mvp-p noise 20 mhz bandwidth 75 150 switching frequency full load, nominal input 100 125 160 khz note: 1. all specifications measured at ta=25c, humidity <75%, nominal input voltage and rated output load unless otherwise sp ecified. model input voltage output output current load nominal range voltage max. min. efficiency regulation ul60950-1 vat1-s5-d5-smt 5 vdc 4.5~5.5 vdc 5 vdc 100 ma 10 ma 72% 10~15% yes vat1-s5-d9-smt 5 vdc 4.5~5.5 vdc 9 vdc 56 ma 6 ma 75% 6.5~15% yes vat1-s5-d12-smt 5 vdc 4.5~5.5 vdc 12 vdc 42 ma 5 ma 78% 6~15% yes vat1-s5-d15-smt 5 vdc 4.5~5.5 vdc 15 vdc 33 ma 4 ma 79% 6~15% yes vat1-s12-d5-smt 12 vdc 10.8~13.2 vdc 5 vdc 100 ma 10 ma 74% 10~15% yes vat1-s12-d9-smt 12 vdc 10.8~13.2 vdc 9 vdc 56 ma 6 ma 76% 6.5~15% yes vat1-s12-d12-smt 12 vdc 10.8~13.2 vdc 12 vdc 42 ma 5 ma 78% 6~15% yes vat1-s12-d15-smt 12 vdc 10.8~13.2 vdc 15 vdc 33 ma 4 ma 79% 6~15% yes vat1-s24-d5-smt 24 vdc 21.6~26.4 vdc 5 vdc 100 ma 10 ma 72% 10~15% no vat1-s24-d9-smt 24 vdc 21.6~26.4 vdc 9 vdc 56 ma 6 ma 74% 6.5~15% no vat1-s24-d12-smt 24 vdc 21.6~26.4 vdc 12 vdc 42 ma 5 ma 76% 6~15% no vat1-s24-d15-smt 24 vdc 21.6~26.4 vdc 15 vdc 33 ma 4 ma 77% 6~15% no vat1-s24-d24-smt 24 vdc 21.6~26.4 vdc 24 vdc 21 ma 2 ma 78% 6~15% no *va(x)t1-series with alt pin config. (see dimensions, page 2)
rev. page date description: dc-dc converter 2 of 3 01/2011 20050 sw 112 th ave. tualatin, oregon 97062 p h o n e phone 503.612.2300 f a x www.v-infinity.com fax 503.612.2383 series: vat1-smt general specifications short circuit protection <1 second temperature rise at full load 25c max, 15c typ. cooling free air convection operating temperature range -40c to +85c storage temperature range -55c to +125c soldering temperature 260c (1.5mm from case for 10 sec.) storage humidity range <95% case material plastic (ul94-v0) safety 2 approved to ul60950-1 (e222736) mtbf >3,500,000 hrs. note: 2. see table on page 1 for available models isolation specifications item test conditions min. typ. max. units isolation voltage tested for 1 min. 1000 vdc insulation resistance test at 500 vdc 1000 m dimensions (mm) com com typical characteristics
rev. page date description: dc-dc converter 3 of 3 01/2011 20050 sw 112 th ave. tualatin, oregon 97062 p h o n e phone 503.612.2300 f a x www.v-infinity.com fax 503.612.2383 series: vat1-smt application notes: - input filtering to reduce the reflected ripple current and minimize emi, especially when the converter input is more than 2 away from the dc source, it is recommended to connect a low esr electrolytic capacitor between vin and gnd. the values suggested are as shown in table 1. if additional filtering is required, the capacitance may be increased, or expanded to an lc network as shown in figure 1. input voltage external input capacitance 4.7 f 5 v 12 v 2.2 f 24 v 1.0 f table 1 vout external ouput capacitance 4.7 f 5 v 9 v 2.2 f 12 v 1.0 f 15 v 0.47 f 24 v 0.33 f table 2 figure 1 +vin -vin +vout com dc c l l dc l c c -vout +vin +vin -vin reg +vout -vout com +vout dc dc dc dc reg reg com -vout reg
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